Formal Models for VHDL
This project explores the construction of formal semantic models for
manipulating VHDL descriptions (To avoid confusion in this work, the
usual phrase "VHDL model" is replaced with "VHDL description".).
Fully elaborated VHDL is assumed and two semantic models are being
constructed, namely: a static model and a dynamic model.
In addition, the project explores the construction of (i) axioms to
define well-formed VHDL descriptions and (ii) rewriting rules that
preserve the semantic behaviors of a VHDL model. Lastly, the project
investigations include the use of the formal models in the
optimization of CAD tools --- specifically optimistically synchronized
parallel simulation of VHDL.
This project is part of the ARPA program titled Rapid Prototyping
of Application Specific Signal Processors (RASSP). The project is
monitored by the Air Force Wright Laboratory.
Additional information of this project.
Last revised: May 12, 1997