Digital Design Environments Lab

Digital Design Environments Laboratory

Research

Research in the Digital Design Environments Laboratory (DDEL) centers around the construction of computer-aided design tools and design environments for analog, digital and mixed-signal systems design. DDEL research has been funded in part by the Advanced Research Projects Agency (ARPA/CSTO and ARPA/ESTO), Wright Labs of the US Air Force, the Semiconductor Research Corporation (SRC), Rome Lab of the US Air Force, and the General Electric Company.

Analog , Mixed-Signal and RF Synthesis and Performance Macro-modeling

• Layout inclusive performance macro-modeling
• Layout inclusive Analog circuit synthesis
• Symbolic Performance Modeling of Analog Circuits
• Symbolic Time Domain Analysis
• Symbolic Sensitivity Analysis
• Interval Fuzzy Valued performance modeling
• Evolutionary circuit topology and synthesis
• Behavioral modeling

Interconnect Modeling and Efficient Routing Topology Generation

• Constraints Satisfying non-linear algorithms for Route Determination.

Design for Manufacturability and Design for Yield

• Intra-gate process variation tolerance modeling
• Process variation tolerant standard cell library
• Negative Bias Temperature Instability tolerance
• Variation aware performance macro modeling of analog circuits
• Variation aware timing analysis

High-Level Synthesis and Formal Verification

• Adaptive Computing and Formal Verification Techniques

Reconfigurable Computing and FPGAs

• Low Power and Battery Powered FPGA Designs
• Network on Chips and Power reduction techniques.
• Performance and communication in FPGA.
• FPGA Synthesis
• Asynchronous FPGA Architectures
• IP Protection and Fault Tolerance in FPGAs.
• Online Scheduling, placement and Routing for FPGAs.
• RC for wireless and Ad-Hoc networks.
• New Router architectures.

Past Projects

• High-Level VLSI Synthesis From VHDL Specifications
  • Distributed Synthesis System - Behavioral Synthesis
  • Low-Power Synthesis
  • User Document: Behavioral VHDL to FPGA Bitmap
• Reconfigurable Computer Systems
  • SPARCS - Synthesis and Partitioning for Adaptive and Reconfigurable Computer Systems
• Performance Specification and Verification
  • PDL -- Performance Description Language
  • Performance Verification Using PDL
  • Formal Verification
• Performance Modeling and Analysis of Adaptive Computing Systems
  • The ARC Project - Analysis of Reconfigurable Computers
• Tools for MCM Design and Synthesis
  • Genetic Algorithms for Partitioning, Placement, and Layer Assignment of MCMs
  • Multicomponent Synthesis
• WAVES Usage, Tools, and Practice
  • Waves usage and examples
• Mixed Signal Synthesis
  • VASE - Mixed Signal Synthesis
• Logic Design Synthesis for Hardware Coprocessor
  • Comet - Logic Design Synthesis

Working Hard