Digital Design Environments Lab

DDEL Publications

Publications (To Appear):

Almitra Pradhan and Ranga Vemuri, "On the Use of Hash Tables for Efficient Analog Circuit Synthesis", in Proc. 21st International Conference on VLSI Design, January 2008

Almitra Pradhan and Ranga Vemuri, "Fast Analog Circuit Synthesis Using Sensitivity Based Near Neighbor Searches", in Proc. 11th International Conference on Design Automation and Test in Europe, March 2008

Current papers not in DBLP:

Almitra Pradhan and Ranga Vemuri, "Regression based circuit matrix models for accurate performance estimation of analog circuits,” in Proc. 15th International IFIP Conference on VLSI-SOC, October 2007, pp. 48–53.

Current DBLP dump of select DDEL papers:

2007
154	EE	Angan Das, Ranga Vemuri: GAPSYS: A GA-based Tool for Automated Passive Analog Circuit Synthesis. ISCAS 2007: 2702-2705
153	EE	Shubhankar Basu, Priyanka Thakore, Ranga Vemuri: Process Variation Tolerant Standard Cell Library Development Using Reduced Dimension Statistical Modeling and Optimization Techniques. ISQED 2007: 814-820
152	EE	Angan Das, Ranga Vemuri: An Automated Passive Analog Circuit Synthesis Framework using Genetic Algorithms. ISVLSI 2007: 145-152
151	EE	Shubhankar Basu, Ranga Vemuri: Process Variation and NBTI Tolerant Standard Cells to Improve Parametric Yield and Lifetime of ICs. ISVLSI 2007: 291-298
150	EE	Huiying Yang, Ranga Vemuri: Efficient Symbolic Sensitivity based Parasitic-Inclusive Optimization in Layout Aware Analog Circuit Synthesis. VLSI Design 2007: 201-206
149	EE	Balasubramanian Sethuraman, Ranga Vemuri: A Force-directed Approach for Fast Generation of Efficient Multi-Port NoC Architectures. VLSI Design 2007: 419-426
2006
148	EE	Renqiu Huang, Ranga Vemuri: Transformation synthesis for data intensive applications to FPGAs. ACM Great Lakes Symposium on VLSI 2006: 349-352
147	EE	Huiying Yang, Ranga Vemuri: Efficient temperature-dependent symbolic sensitivity analysis and symbolic performance evaluation in analog circuit synthesis. DATE 2006: 283-284
146	EE	Balasubramanian Sethuraman, Ranga Vemuri: optiMap: a tool for automated generation of noc architectures using multi-port routers for FPGAs. DATE 2006: 947-952
145	EE	Balasubramanian Sethuraman, Ranga Vemuri: Multi2 Router: A Novel Multi Local Port Router Architecture with Broadcast Facility for FPGA-Based Networks-on-Chip. FPL 2006: 1-4
144	EE	Xin Jia, Ranga Vemuri: Studying a GALS FPGA architecture using a parameterized automatic design flow. ICCAD 2006: 688-693
143	EE	Mukesh Ranjan, Ranga Vemuri: Exact hierarchical symbolic analysis of large analog networks using a general interconnection template. ISCAS 2006
142	EE	Vijay Sundaresan, Ranga Vemuri: A Novel Approach to Performance-Oriented Datapath Allocation and Floorplanning. ISVLSI 2006: 323-328
141	EE	Amitava Bhaduri, Ranga Vemuri: Parasitic Aware Routing Methodology Based on Higher Order RLCK Moment Metrics. VLSI Design 2006: 141-146
140	EE	Xin Jia, Ranga Vemuri: CAD Tools for a Globally Asynchronous Locally Synchronous FPGA Architecture. VLSI Design 2006: 251-256
139	EE	Mengmeng Ding, Ranga Vemuri: Efficient Analog Performance Macromodeling via Sequential Design Space Decomposition. VLSI Design 2006: 553-556
138	EE	Ritochit Chakraborty, Mukesh Ranjan, Ranga Vemuri: Symbolic Time-Domain Behavioral and Performance Modeling of Linear Analog Circuits Using an Efficient Symbolic Newton-Iteration Algorithm for Pole Extraction. VLSI Design 2006: 689-694
137	EE	Nagu R. Dhanwada, Alex Doboli, Adrián Núñez-Aldana, Ranga Vemuri: Hierarchical constraint transformation based on genetic optimization for analog system synthesis. Integration 39(3): 267-290 (2006)
2005
136	EE	Amitava Bhaduri, Ranga Vemuri: Moment-driven coupling-aware routing methodology. ACM Great Lakes Symposium on VLSI 2005: 390-395
135	EE	Balasubramanian Sethuraman, Prasun Bhattacharya, Jawad Khan, Ranga Vemuri: LiPaR: A light-weight parallel router for FPGA-based networks-on-chip. ACM Great Lakes Symposium on VLSI 2005: 452-457
134	EE	Anuradha Agarwal, Glenn Wolfe, Ranga Vemuri: Accuracy driven performance macromodeling of feasible regions during synthesis of analog circuits. ACM Great Lakes Symposium on VLSI 2005: 482-487
133	EE	Xin Jia, Ranga Vemuri: Using GALS architecture to reduce the impact of long wire delay on FPGA performance. ASP-DAC 2005: 1260-1263
132	EE	Huiying Yang, Mukesh Ranjan, Wim Verhaegen, Mengmeng Ding, Ranga Vemuri, Georges G. E. Gielen: Efficient symbolic sensitivity analysis of analog circuits using element-coefficient diagrams. ASP-DAC 2005: 230-235
131	EE	Mengmeng Ding, Glenn Wolfe, Ranga Vemuri: An error-driven adaptive grid refinement algorithm for automatic generation of analog circuit performance macromodels. ASP-DAC 2005: 477-482
130	EE	Mengmeng Ding, Ranga Vemuri: A combined feasibility and performance macromodel for analog circuits. DAC 2005: 63-68
129	EE	Mengmeng Ding, Ranga Vemuri: A Two-Level Modeling Approach to Analog Circuit Performance Macromodeling. DATE 2005: 1088-1089
128	EE	Raoul F. Badaoui, Ranga Vemuri: Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis. DATE 2005: 138-143
127	EE	Jawad Khan, Ranga Vemuri: An Iterative Algorithm for Battery-Aware Task Scheduling on Portable Computing Platforms. DATE 2005: 622-627
126	EE	Amitava Bhaduri, Ranga Vemuri: Inductive and Capacitive Coupling Aware Routing Methodology Driven by a Higher Order RLCK Moment Metric. DATE 2005: 922-923
125	EE	Xin Jia, Ranga Vemuri: The GAPLA: A Globally Asynchronous Locally Synchronous FPGA Architecture. FCCM 2005: 291-292
124		Xin Jia, Ranga Vemuri: A Novel Asynchronous FPGA Architecture Design and Its Performance Evaluation. FPL 2005: 287-292
123		Jawad Khan, Ranga Vemuri: Energy Management in Battery-Powered Sensor Networks with Reconfigurable Computing Nodes. FPL 2005: 543-546
122		Renqiu Huang, Ranga Vemuri: PAHLS: Towards Run-Time Synthesis for FPGAs. FPL 2005: 739-740
121		Anuradha Agarwal, Ranga Vemuri: Hierarchical performance macromodels of feasible regions for synthesis of analog and RF circuits. ICCAD 2005: 430-436
120	EE	Anuradha Agarwal, Ranga Vemuri: Layout-Aware RF Circuit Synthesis Driven by Worst Case Parasitic Corners. ICCD 2005: 444-452
119	EE	Jawad Khan, Ranga Vemuri: Battery-Efficient Task Execution on Reconfigurable Computing Platforms with Multiple Processing Units. IPDPS 2005
118	EE	Raoul F. Badaoui, Ranga Vemuri: Analog VLSI circuit-level synthesis using multi-placement structures. ISCAS (6) 2005: 5978-5981
117	EE	Renqiu Huang, Ranga Vemuri: Sensitivity Analysis of a Cluster-Based Interconnect Model for FPGAs. ISVLSI 2005: 250-251
116	EE	Huiying Yang, Anuradha Agarwal, Ranga Vemuri: Fast Analog Circuit Synthesis Using Multiparameter Sensitivity Analysis Based on Element-Coefficient Diagrams. ISVLSI 2005: 71-76
115	EE	Mengmeng Ding, Ranga Vemuri: An Active Learning Scheme Using Support Vector Machines for Analog Circuit Feasibility Classification. VLSI Design 2005: 528-534
114	EE	Madhubanti Mukherjee, Ranga Vemuri: On Physical-Aware Synthesis of Vertically Integrated 3D Systems. VLSI Design 2005: 647-652
113	EE	Renqiu Huang, Ranga Vemuri: On-Line Synthesis for Partially Reconfigurable FPGAs. VLSI Design 2005: 663-668
2004
112	EE	Raoul F. Badaoui, Hemanth Sampath, Anuradha Agarwal, Ranga Vemuri: A high level language for pre-layout extraction in parasite-aware analog circuit synthesis. ACM Great Lakes Symposium on VLSI 2004: 271-276
111	EE	Anuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri: Fast and accurate parasitic capacitance models for layout-aware. DAC 2004: 145-150
110	EE	Manish Handa, Ranga Vemuri: An efficient algorithm for finding empty space for online FPGA placement. DAC 2004: 960-965
109	EE	Anuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri: Accurate Estimation of Parasitic Capacitances in Analog Circuits. DATE 2004: 1364-1365
108	EE	Mukesh Ranjan, Wim Verhaegen, Anuradha Agarwal, Hemanth Sampath, Ranga Vemuri, Georges G. E. Gielen: Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models. DATE 2004: 604-609
107	EE	Manish Handa, Ranga Vemuri: A Fast Algorithm for Finding Maximal Empty Rectangles for Dynamic FPGA Placement. DATE 2004: 744-745
106		Jawad Khan, Jayanthi Rajagopalan, Renqiu Huang, Ranga Vemuri: A Portable Face Recognition System Using Reconfigurable Hardware. ERSA 2004: 213-217
105		Jawad Khan, Balasubramanian Sethuraman, Ranga Vemuri: A Power-Performance Trade-off Methodology for Portable Reconfigurable Platforms. ERSA 2004: 33-37
104		Manish Handa, Ranga Vemuri: Area Fragmentation in Reconfigurable Operating Systems. ERSA 2004: 77-83
103		Xin Jia, Ranga Vemuri: A Design Methodology for Self-Timed Event Logic Pipelines. ESA/VLSI 2004: 475-479
102	EE	Manish Handa, Ranga Vemuri: An Integrated Online Scheduling and Placement Methodology. FPL 2004: 444-453
101	EE	Jawad Khan, Ranga Vemuri: An Efficient Battery-Aware Task Scheduling Methodology for Portable RC Platforms. FPL 2004: 669-678
100	EE	Xin Jia, Jayanthi Rajagopalan, Ranga Vemuri: A Dynamically Reconfigurable Asynchronous FPGA Architecture. FPL 2004: 836-841
99	EE	Renqiu Huang, Manish Handa, Ranga Vemuri: Analysis of a Hybrid Interconnect Architecture for Dynamically Reconfigurable FPGAs. FPL 2004: 900-905
98	EE	Renqiu Huang, Ranga Vemuri: Analysis and evaluation of a hybrid interconnect structure for FPGAs. ICCAD 2004: 595-601
97	EE	Ranga Vemuri, Glenn Wolfe: Adaptive sampling and modeling of analog circuit performance parameters with pseudo-cubic splines. ICCAD 2004: 931-938
96	EE	Madhubanti Mukherjee, Ranga Vemuri: Simultaneous Scheduling, Binding and Layer Assignment for Synthesis of Vertically Integrated 3D Systems. ICCD 2004: 222-227
95	EE	Renqiu Huang, Ranga Vemuri: Forward-Looking Macro Generation and Relational Placement During High Level Synthesis to FPGAs. IPDPS 2004
94	EE	Manish Handa, Ranga Vemuri: Hardware Assisted Two Dimensional Ultra Fast Placement. IPDPS 2004
93	EE	Alex Doboli, Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri: A two-layer library-based approach to synthesis of analog systems from VHDL-AMS specifications. ACM Trans. Design Autom. Electr. Syst. 9(2): 238-271 (2004)
2003
92	EE	Madhubanti Mukherjee, Ranga Vemuri: A Novel Synthesis Strategy Driven by Partial Evaluation Based Circuit Reduction for Application Specific DSP Circuits. ICCD 2003: 436-440
91	EE	Manish Handa, Rajesh Radhakrishnan, Madhubanti Mukherjee, Ranga Vemuri: A Fast Macro Based Compilation Methodology for Partially Reconfigurable FPGA Designs. VLSI Design 2003: 91-
90		Glenn Wolfe, Mengmeng Ding, Ranga Vemuri: Adaptive Sampling and Modeling of Analog Circuit Performance Parameters. VLSI-SOC 2003: 142-
89		Hemanth Sampath, Ranga Vemuri: MSL: A High-Level Language for Parameterized Analog and Mixed Signal Layout Generators. VLSI-SOC 2003: 416-421
88	EE	Alex Doboli, Ranga Vemuri: Behavioral modeling for high-level synthesis of analog and mixed-signal systems from VHDL-AMS. IEEE Trans. on CAD of Integrated Circuits and Systems 22(11): 1504-1520 (2003)
87	EE	Alex Doboli, Ranga Vemuri: Exploration-based high-level synthesis of linear analog systems operating at low/medium frequencies. IEEE Trans. on CAD of Integrated Circuits and Systems 22(11): 1556-1568 (2003)
86	EE	Glenn Wolfe, Ranga Vemuri: Extraction and use of neural network models in automated synthesis of operational amplifiers. IEEE Trans. on CAD of Integrated Circuits and Systems 22(2): 198-212 (2003)
2002
85	EE	Srinivasan Dasasathyan, Rajesh Radhakrishnan, Ranga Vemuri: Framework for Synthesis of Virtual Pipelines. ASP-DAC 2002: 326-331
84	EE	Alex Doboli, Ranga Vemuri: A Functional Specification Notation for Co-Design of Mixed Analog-Digital Systems. DATE 2002: 760-769
83	EE	Jawad Khan, Manish Handa, Ranga Vemuri: iPACE-V1: A Portable Adaptive Computing Engine for Real Time Applications. FPL 2002: 69-78
82	EE	Srinivasan Dasasathyan, Rajesh Radhakrishnan, Ranga Vemuri: Framework for Synthesis of Virtual Pipelines. VLSI Design 2002: 326-331
81	EE	Ranga Vemuri, Srinivas Katkoori, Meenakshi Kaul, Jay Roy: An efficient register optimization algorithm for high-level synthesis from hierarchical behavioral specifications. ACM Trans. Design Autom. Electr. Syst. 7(1): 189-216 (2002)
2001
80	EE	Sree Ganesan, Ranga Vemuri: Analog-Digital Partitioning for Field-Programmable Mixed Signal Systems. ARVLSI 2001: 172-187
79	EE	Rajesh Radhakrishnan, Elena Teica, Ranga Vemuri: Verification of Basic Block Schedules Using RTL Transformations. CHARME 2001: 173-178
78	EE	Karam S. Chatha, Ranga Vemuri: MAGELLAN: multiway hardware-software partitioning and scheduling for latency minimization of hierarchical control-dataflow task graphs. CODES 2001: 42-47
77	EE	Sree Ganesan, Ranga Vemuri: Behavioral Partitioning in the Synthesis of Mixed Analog-Digital Systems. DAC 2001: 133-138
76	EE	Alex Doboli, Ranga Vemuri: Integrated High-Level Synthesis and Power-Net Routing for Digital Design under Switching Noise Constraints. DAC 2001: 629-634
75	EE	Iyad Ouaiss, Ranga Vemuri: Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers. DATE 2001: 650-657
74	EE	Elena Teica, Rajesh Radhakrishnan, Ranga Vemuri: On the verification of synthesized designs using automatically generated transformational witnesses. DATE 2001: 798
73	EE	Alex Doboli, Ranga Vemuri: A regularity-based hierarchical symbolic analysis method for large-scale analog networks. DATE 2001: 806
72	EE	Amit Kasat, Iyad Ouaiss, Ranga Vemuri: Memory Synthesis for FPGA-Based Reconfigurable Computers. FPL 2001: 70-80
71		Yi Pan, Jie Li, Ranga Vemuri: Continous Wavelet Transform on Reconfigurable Meshes. IPDPS 2001: 114
70		Iyad Ouaiss, Ranga Vemuri: Global memory mapping for FPGA-based reconfigurable systems. IPDPS 2001: 144
69	EE	S. Saha, Ranga Vemuri: Use of adaptive integer-to-integer wavelet transforms in lossless image coding. ISCAS (2) 2001: 393-396
68	EE	Alex Doboli, Ranga Vemuri: Hierarchical performance optimization for synthesis of linear analog systems. ISCAS (5) 2001: 431-434
67	EE	Sree Ganesan, Ranga Vemuri: Library Binding for High-Level Synthesis of Analog Systems. VLSI Design 2001: 261-268
66	EE	Sujatha Sundararaman, Sriram Govindarajan, Ranga Vemuri: Application Specific Macro Based Synthesis. VLSI Design 2001: 317-
65		Naren Narasimhan, Elena Teica, Rajesh Radhakrishnan, Sriram Govindarajan, Ranga Vemuri: Theorem Proving Guided Development of Formal Assertions in a Resource-Constrained Scheduler for High-Level Synthesis. Formal Methods in System Design 19(3): 237-273 (2001)
2000
64	EE	Satish Ganesan, Ranga Vemuri: An Integrated Temporal Partitioning and Partial Reconfiguration Technique for Design Latency Improvement. DATE 2000: 320-325
63	EE	Iyad Ouaiss, Ranga Vemuri: Efficient Resource Arbitration in Reconfigurable Computing Environments. DATE 2000: 560-566
62	EE	Sree Ganesan, Ranga Vemuri: Technology Mapping and Retargeting for Field-Programmable Analog Arrays. DATE 2000: 58-
61	EE	Sriram Govindarajan, Ranga Vemuri: Improving the Schedule Quality of Static-List Time-Constrained Scheduling. DATE 2000: 749
60	EE	Sriram Govindarajan, Ranga Vemuri: Tightly Integrated Design Space Exploration with Spatial and Temporal Partitioning in SPARCS. FPL 2000: 7-18
59	EE	Preetham Lakshmikanthan, Sriram Govindarajan, Vinoo Srinivasan, Ranga Vemuri: Behavioral Partitioning with Synthesis for Multi-FPGA Architectures under Interconnect, Area, and Latency Constraints. IPDPS Workshops 2000: 924-931
58	EE	Sriram Govindarajan, Vinoo Srinivasan, Preetham Lakshmikanthan, Ranga Vemuri: A Technique for Dynamic High-Level Exploration During Behavioral-Partitioning for Multi-Device Architectures. VLSI Design 2000: 212-219
57	EE	Abhijit Ghosh, Ranga Vemuri: Formal Verification of Synthesized Mixed Signal Designs Using *BMDs. VLSI Design 2000: 84-
56		Nazanin Mansouri, Ranga Vemuri: Automated Correctness Condition Generation for Formal Verification of Synthesized RTL Designs. Formal Methods in System Design 16(1): 59-91 (2000)
55		Ranga Vemuri, Randolph E. Harr: Configurable Computing: Technology and Applications - Guest Editors' Introduction. IEEE Computer 33(4): 39-40 (2000)
1999
54	EE	Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri: Automatic Constraint Transformation with Integrated Parameter Space Exploration in Analog System Synthesis. ASP-DAC 1999: 153-156
53	EE	Meenakshi Kaul, Ranga Vemuri, Sriram Govindarajan, Iyad Ouaiss: An Automated Temporal Partitioning and Loop Fission Approach for FPGA Based Reconfigurable Synthesis of DSP Applications. DAC 1999: 616-622
52	EE	Alex Doboli, Adrián Núñez-Aldana, Nagu R. Dhanwada, Sree Ganesan, Ranga Vemuri: Behavioral Synthesis of Analog Systems Using Two-layered Design Space Exploration. DAC 1999: 951-957
51	EE	Meenakshi Kaul, Ranga Vemuri: Temporal Partitioning combined with Design Space Exploration for Latency Minimization of Run-Time Reconfigured Designs. DATE 1999: 202-209
50	EE	Nazanin Mansouri, Ranga Vemuri: Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs. DATE 1999: 223-
49	EE	Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri: Hierarchical Constraint Transformation Using Directed Interval Search for Analog System Synthesis. DATE 1999: 328-
48	EE	Alex Doboli, Ranga Vemuri: A VHDL-AMS Compiler and Architecture Generator for Behavioral Synthesis of Analog Systems. DATE 1999: 338-345
47	EE	Adrián Núñez-Aldana, Ranga Vemuri: An Analog Performance Estimator for Improving the Effectiveness of CMOS Analog Systems Circuit Synthesis. DATE 1999: 406-411
46	EE	Vinoo Srinivasan, Ranga Vemuri: Task-Level Partitioning and RTL Design Space Exploration for Multi-FPGA Architectures. FCCM 1999: 272-
45	EE	Vinoo Srinivasan, Ranga Vemuri: Throughput Optimization with Design Space Exploration During Partitioning for Multi-FPGA Architectures. FPGA 1999: 253
44		Karam S. Chatha, Ranga Vemuri: Hardware-Software Codesign for Dynamically Reconfigurable Architectures. FPL 1999: 175-184
43