CS122: Information on Using Makefiles

The UNIX make command helps to automate many tedious processes associated with software development. The make program follows a user-prepared description file known as a makefile. The contents of the makefile include all the file dependencies that exist among the components of a software system. Makefiles consist of dependencies of the form:

target:  components
TAB      command rule

So for example a makefile containing:

myprog: x.o lib.o 
        g++ -o myprog x.o lib.o 

x.o:    x.cpp x.h
        g++ -c x.cpp

lib.o:  lib.c lib.h
        g++ -c lib.cpp

has three targets, each target having two components on which it depends. Typing the command "%make " will update all the targets which have components that have changed.

Here is another sample makefile which uses macros. We will discuss both these examples in class, and we will show how you can effectively use makefiles for your homework assignments. Makfiles should also be submitted with your homework, to allow the TA to compile and grade your projects.